Freescale Semiconductor /MKM34Z7 /SIM /CLKDIV1

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Interpret as CLKDIV1

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)FLASHCLKMODE 0 (00)CLKDIVBUS 0 (0000)CLKDIVSYS

CLKDIVSYS=0000, FLASHCLKMODE=0, CLKDIVBUS=00

Description

System Clock Divider Register 1

Fields

FLASHCLKMODE

Flash Clock Mode

0 (0): Flash Clock is the same as BUS clock.

1 (1): Flash Clock is a half of BUS clock.

CLKDIVBUS

Bus Clock divider

0 (00): SYSCLK:BUSCLK = 1:1

1 (01): SYSCLK:BUSCLK = 2:1

2 (10): SYSCLK:BUSCLK = 3:1

3 (11): SYSCLK:BUSCLK = 4:1

CLKDIVSYS

System Clock divider

0 (0000): Divide by 1

1 (0001): Divide by 2

2 (0010): Divide by 3

3 (0011): Divide by 4 and so on… If FOPT[0] is 0, the divider is set to div-by-8 after system reset is deasserted (after completion of system initialization sequence).

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